This invention relates to integrated semiconductor devices and methods of manufacture, and more particularly to an improved method of making N-channel insulated gate field effect transistors in integrated circuit form.
Most MOS memory and processor type devices now being manufactured are N-channel of speed, circuit density and cost factors which heretofore have favored NMOS over P-channel. Established N-channel self-aligned gate processes are quite successful in large volume manufacture. However, one problem with the standard N-channel processes is that diffused N+ regions cannot be used as interconnects beneath polysilicon because whenever poly crosses moat a transistor is formed. This is because the poly and its underlying gate oxide provide the diffusion or implant mask for defining the N+ regions.
As an improvement in the NMOS process, it has been found that significant advantages result in a method which employs formation of N+ diffused regions prior to defining the poly gates, then self-aligning implants adjacent each gate in the source-drain areas as will be explained.
It is the principal object of this invention to provide improved NMOS circuit devices and an improved method of making such devices. Another object is to provide integrated circuit devices and methods of making devices which allow the speed advantage of N-channel transistors to be utilized, and which provide smaller size or higher circuit density with higher speed and/or lower cost. A further object is to provide NMOS devices which have self-aligned gates and yet allow polysilicon to cross over moat regions without forming transistors.